The present invention relates to a timing control device and a control method thereof, and more particularly, to a timing control device suitable for versatile timing control, and a control method thereof.
Along with the recent diversification of applications, there is a demand for controlling a plurality of control targets, such as an engine and a motor, using a single microcomputer. Existing microcomputers generally include timers exclusively used for the respective control targets. In other words, the existing microcomputers generally include a number of timers corresponding to the number of control targets. Therefore, the existing microcomputers have a problem of an increase in circuit size.
Japanese Unexamined Patent Application Publication Nos. 09-139732 and 09-171418 disclose countermeasures against such a problem. FIG. 16 is a block diagram showing a timing signal generator disclosed in Japanese Unexamined Patent Application Publication No. 09-139732. The timing signal generator shown in FIG. 16 is a device that detects a coincidence between a value counted by a timer 11 and a designated temporal position, and generates a timing signal. This timing signal generator includes a memory unit 13 that stores a plurality of positional information items to designate a temporal position of a change point of the timing signal, and a plurality of output control information items to designate an output terminal for the timing signal and a signal change at the change point; a coincidence detection unit 14 that generates a coincidence detection pulse when the positional information and the timer value coincide with each other; an output control unit 17 that generates a timing signal designated based on the output control information read from the memory and the coincidence detection pulse; and an address counter unit 15 that generates an address signal of corresponding subsequent information for the memory when the coincidence detection pulse is output. This configuration enables generation of a number of timing signals only by using a single coincidence detection unit.
Thus, the timing signal generator shown in FIG. 16 need not include a plurality of coincidence detection units even in the case of generating a number of timing signals. This results in suppression of an increase in circuit size.
FIG. 17 is a block diagram showing a timer/counter circuit disclosed in Japanese Unexamined Patent Application Publication No. 09-171418. The timer/counter circuit shown in FIG. 17 includes an incrementer 1, a latch circuit 2, a register block 3A, a coincidence flag 4A, a clear control unit 5, an operation control unit 6, a central processing unit 7, a data bus 8, an internal bus 9, and a transfer control circuit 10. The register block 3A includes a buffer circuit 30, counters 31A to 31D, a timer register 32 having a coincidence detection function, and coincident data storage circuits 33A to 33D having no coincidence detection function.
The coincident data storage circuits 33A to 33D store timer values respectively corresponding to the counters 31A to 31D. The transfer control circuit 10 transfers the timer value stored in any of the coincident data storage circuits 33A to 33D to the timer register 32. The timer register 32 detects a coincidence between the timer value transferred from any of the coincident data storage circuits 33A to 33D and the count value of the corresponding counter, and outputs a coincidence signal F. The coincidence flag 4A generates a corresponding interrupt signal (any of IA to ID) according to the coincidence signal F from the timer register 32.
In this manner, the timer/counter circuit shown in FIG. 17 includes a plurality of coincident data storage circuits which are formed of RAM cells having no coincidence detection function and which have a small circuit size, instead of including a plurality of timer registers which are formed of CAM cells having the coincidence detection function and which have a large circuit size. This results in suppression of an increase in circuit size.
Additionally, Japanese Unexamined Patent Application Publication No. 2002-303201 discloses a vehicle control device including a microcomputer. This microcomputer counts values of control counters for use in various controls at predetermined time intervals in a base process. Further, the microcomputer determines an execution timing for each of the various controls based on the counter values, and carries out the corresponding process when the timing is reached. This microcomputer counts up a reference counter in a fixed-time interrupt process, and calculates a delay of the base process by referring to the reference counter at each count-up timing of each control counter. When the delay reaches an operation width for one counting operation by the control counter, the value of the control counter is corrected.
Furthermore, Japanese Unexamined Patent Application Publication No. 2008-169709 discloses an on-vehicle engine control device that generates a pulse width modulation signal to improve the accuracy of authentication/collation of a start key with an inexpensive configuration. In a microprocessor provided in the on-vehicle engine control device, two timer circuit units constitute first and second drive control timers TIM1 and TIM2, respectively, and generate control output signals for controlling ignition/fuel injection which operate in synchronization with a crank angle sensor. The control output signals are distributed to cylinders by a plurality of cylinder selecting gate circuits and sequentially drive respective engine driving devices.
Until completion of the authentication/collation, the pulse width modulation signal generated in the first drive control timer TIM1 is transmitted to an immobilizer through an authentication gate circuit. The immobilizer transmits a radio signal having a frequency and an amplitude corresponding to the cycle and duty of the received pulse width modulation signal to a transponder, and reads a personal identification number from the start key.